Process for forming dual metal gate structures

US6790719B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Olubunmi O. Adetutu · Austin, US
• Eric D. Luckowski · Round Rock, US
• Srikanth B. Samavedam · Austin, US
• Arturo Martinez · Milano, IT

Key dates

• Filing date: Apr 9, 2003
• Grant date: Sep 14, 2004
• Expiry date: Aug 9, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0147

Abstract

A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.