Method of forming source/drain regions in semiconductor devices
US6790735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.