Process for forming barrier/seed structures for integrated circuits
US6790773B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Aug 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1089
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.