Patent · US Expired

MRAM configuration

US6791871B2 · kind B2 · utility

6Cited by

8References

6Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martin Freitag · Munich, DE
Thomas Roehr · Yokohama, JP

Key dates

Filing date	Jul 25, 2003
Grant date	Sep 14, 2004
Priority date	—
Expiry date	Jul 25, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.