Method of calculating the real added defect counts
US6794203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67288
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.