Vertical split gate flash memory cell and method for fabricating the same
US6794250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jun 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6894
Abstract
A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.