Apparatus for reducing soft errors in dynamic circuits
US6794901B2 · kind B2 · utility
20Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.