Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors
US6798069B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1433
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.