System and method to improve the efficiency of synchronous mirror delays and delay locked loops
US6798259B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase detection system and method for use with a synchronous mirror delay (“SMD”) or a delay-locked loop (“DLL”) reduces the number of delay stages required and increases efficiency. The invention takes a clock input signal and clock delay or feedback signal, each having timing characteristics, and differentiates between four conditions based upon timing characteristics of the signals. The phase detector and associated circuitry determines, based upon timing characteristics of the signals, which phase conditions the signals are in. Selectors select the signals to be introduced into the SMD or DLL by the timing characteristics of the phase conditions. The invention utilizes the falling clock edge of the clock input signal and decreases the lock time under specific phase conditions. The invention increases efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.