Method for reducing drain disturb in programming
US6798694B2 · kind B2 · utility
19Cited by
9References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.