Wordline latching in semiconductor memories
US6798712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Oct 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.