Critical dimension statistical process control in semiconductor fabrication
US6799152B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.