Method for fabricating semiconductor device with storage node contact structure
US6800522B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2003 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jul 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/768
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.