Method for manufacturing a self-aligned split-gate flash memory cell
US6800526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.