Integrated circuit configuration having a structure for reducing a minority charge carrier current

US6800925B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ludwig Rossmeier · Dorfen, DE
• Norbert Krischke · Munich, DE
• Wolfgang Werner · Hersbruck, DE
• Peter Nelle · Munich, DE

Key dates

• Filing date: Jan 23, 2003
• Grant date: Oct 5, 2004
• Expiry date: Jan 23, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and a second semiconductor zone of the first conductivity type adjoining the first semiconductor zone and doped more weakly than the first semiconductor zone in a region near a front side, a first component region in the body having at least one semiconductor zone of a second conductivity type, a second component region in the body having at least one semiconductor zone of the second conductivity type, and a conversion structure having a semiconductor zone of the second conductivity type and a semiconductor zone of the first conductivity type that are short-circuited and disposed at a distance from the first semiconductor zone between the first and second component regions in the second semiconductor zone.