Peter Nelle
16Patents
4h-index
15Co-inventors
57Inventor score
Filing activity: Dec 13, 1991 → Sep 23, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5315121A | Metal ion source and a method of producing metal ions | Electricity | 11 | Expired |
| US6800925B2 | Integrated circuit configuration having a structure for reducing a minority charge carrier current | Electricity | 7 | Expired |
| US8803297B2 | Semiconductor device including a stress relief layer and method of manufacturing | Electricity | 6 | Active |
| US9184284B2 | Method for operating field-effect transistor, field-effect transistor and circuit configuration | Electricity | 6 | Active |
| US9455205B2 | Semiconductor devices and processing methods | Electricity | 3 | Active |
| US9218960B2 | Method of manufacturing a semiconductor device including a stress relief layer | Electricity | 2 | Active |
| US9099419B2 | Test method and test arrangement | Electricity | 2 | Active |
| US7888782B2 | Apparatus and method configured to lower thermal stresses | Electricity | 2 | Active |
| US8021929B2 | Apparatus and method configured to lower thermal stresses | Electricity | 1 | Active |
| US6894367B2 | Vertical bipolar transistor | Electricity | 1 | Expired |
| US8188592B2 | Apparatus and method configured to lower thermal stresses | Electricity | 0 | Active |
| US9343565B2 | Semiconductor device having a dense trench transistor cell array | Electricity | 0 | Active |
| US9054150B2 | Chip edge sealing | Electricity | 0 | Active |
| US9429616B2 | Test method and test arrangement | Electricity | 0 | Active |
| US7943960B2 | Integrated circuit arrangement including a protective structure | Electricity | 0 | Active |
| US9165921B2 | Transistor cell array including semiconductor diode | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.