Method for laminating and mounting semiconductor chip
US6803253B2 · kind B2 · utility
2Cited by
6References
17Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of semiconductor chips each having an electrode surface are sequentially laminated and mounted. Initially, the electrode surfaces of the semiconductor chips are activated. Then, the semiconductor chips are positioned. Successively, the semiconductor chips are laminated and bonded by pressing such that a reaction layer is not formed or formation of the reaction layer is suppressed excessively. Finally, the semiconductor chips are entirely heated so as to form the reaction layer after lamination and bonding of all the semiconductor chips are completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.