Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliability
US6803653B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2001 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Nov 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein:bending stiffness=Et3, with E=Young's modulus, and t=thickness.In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.