Method for testing integrated logic circuits
US6804803B2 · kind B2 · utility
3Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.