Method of balanced coefficient of thermal expansion for flip chip ball grid array
US6806119B2 · kind B2 · utility
1Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.