Semiconductor integrated circuit device and a method of manufacturing the same
US6806128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2001 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jul 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
With a gate electrode and side wall spacers being used as masks, ions of an n-type impurity are implanted from the normal line direction of a substrate, whereby source/drain diffused regions are formed. Then, ions of an n-type impurity are introduced by oblique implantation having a predetermined angle relative to the normal line direction of the substrate to form an n-type semiconductor region having an impurity concentration higher than source/drain extended regions. By this method, the junction depth of the semiconductor region becomes smaller than that of the source/drain diffused regions and greater than that of the source/drain extended regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.