Method of forming integrated circuitry, and method of forming a contact opening

US6806197B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Shane J. Trapp · Boise, US
• Brian F. Lawlor · Boise, US

Key dates

• Filing date: Aug 7, 2001
• Grant date: Oct 19, 2004
• Expiry date: Nov 29, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.