Method of forming a dual damascene structure using an amorphous silicon hard mask
US6806203B2 · kind B2 · utility
24Cited by
29References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.