Field effect transistor with improved isolation structures
US6806541B2 · kind B2 · utility
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10References
4Claims
0Family size
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Key dates
| Filing date | Mar 1, 2004 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Mar 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76216
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.