Semiconductor memory device
US6807101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.