Semiconductor memory with shadow memory cell
US6807107B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | May 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.