Method for forming isolation in flash memory wafer
US6808988B1 · kind B1 · utility
4Cited by
4References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 5, 1998 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Feb 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a self-aligned isolated memory core for a flash memory wafer includes the steps of establishing control gates for memory cells in the core by depositing a first polysilicon layer on a silicon substrate, etching the first layer, and depositing a second polysilicon layer on the substrate, with the polysilicon layers being separated by an interpoly dielectric layer. Then, after the control gates have been established, isolation trenches are formed in the silicon substrate between regions by self-aligned etching processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.