Method and system for tailoring core and periphery cells in a nonvolatile memory

US6808992B1 · kind B1 · utility

Assignee

• Spansion LLC. · US

Inventors

• Kelwin Ko · San Jose, US
• Shenqing Fang · Fremont, US
• Angela T. Hui · Fremont, US
• Hiroyuki Kinoshita · San Jose, US
• Wenmei Li · San Jose, US
• Yu Sun · Saratoga, US
• Hiroyuki Ogawa · Nagoya, JP

Key dates

• Filing date: May 15, 2002
• Grant date: Oct 26, 2004
• Expiry date: May 15, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.