Semiconductor integrated circuit device and process for manufacturing the same
US6809399B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Dec 26, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer.Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.