Gate-equivalent-potential circuit and method for I/O ESD protection
US6809915B2 · kind B2 · utility
4Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/814
Abstract
A gate-equivalent-potential circuit and method for an I/O pad ESD protection arrangement including used and unused MOS fingers connected to the I/O pad comprises a switch connected between the gates of the MOS fingers, an ESD detector connected to the switch to turn on the switch upon an ESD event and a gate-modulated circuit connected to the gate of the unused finger to couple a voltage thereto to reduce the triggering voltage of the transistors within the fingers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.