Non-volatile semiconductor memory device capable of rapid operation
US6809969B2 · kind B2 · utility
2Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At a time a voltage of 6V is applied to all word lines and memory cells connected to a bit line are all simultaneously subjected to a weak write operation using a channel hot electron. Furthermore at a subsequent time a voltage of approximately 2V is applied to a word line and any single memory cell connected to the word line is subjected to a verify operation. The series of the weak write and verify operations are repeated until this memory cell's threshold voltage attains 2V corresponding to an erased condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.