Circuit technique for column redundancy fuse latches
US6809972B2 · kind B2 · utility
3Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.