Delay locked loop control circuit
US6809990B2 · kind B2 · utility
23Cited by
12References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Jun 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.