Microprocessor and method for performing selective prefetch based on bus activity level
US6810466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor that selectively performs prefetch instructions based upon an indication of future processor bus activity and cache line status. The microprocessor includes a programmable threshold register for storing a threshold value. The threshold value is such that if the depth of bus requests queued in the bus interface unit of the microprocessor is greater than the threshold value, this condition indicates a high likelihood of a high level of bus activity in the near future, for example due to a workload change. If a prefetch instruction cache line address misses in the processor cache, then the line is not prefetched from external memory unless the line may be supplied from one level of internal cache to a lower level of internal cache. However, even in this case the line is not transferred internally if the line status is shared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.