Method of fabricating a self-aligned via contact for a magnetic memory element
US6812040B2 · kind B2 · utility
17Cited by
6References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.