Method and system for performing failure analysis on a multilayer silicon-on-insulator (SOI) device
US6812049B1 · kind B1 · utility
4Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jan 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2898
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for performing backside analysis on a silicon-on-insulator (SOI) device is disclosed. The SOI device includes a silicon layer, a buried oxide layer (BOX), an active layer containing active devices, and multiple metal layers. The method includes opening a window in the silicon layer using the BOX layer as a stop, and using the window as a field of view to view structures in the active layer with a microscope, wherein defects can be detected in the device without delayering any of the metal layers, such that the device remains functional for testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.