Source drain and extension dopant concentration

US6812073B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Haowen Bu · Plano, US
• Amitabh Jain · Allen, US
• Wayne Bather · Plano, US
• Stephanie W. Butler · Richardson, US

Key dates

• Filing date: Dec 10, 2002
• Grant date: Nov 2, 2004
• Expiry date: Jan 5, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.