Fabrication method for non-volatile memory
US6812083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jun 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a well. The method further includes biasing the first MOS with a first biasing voltage to actuate the first MOS transistor, biasing the second MOS transistor with a second biasing voltage to enable the second MOS transistor to generate a gate current, and adjusting capacitances between the floating gate of the second MOS transistor and the drain, the source, the control gate, and the well according to voltage difference between the floating gate of the second MOS transistor and the source of the second MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.