Method of forming semiconductor device including silicon oxide with fluorine, embedded wiring layer, via holes, and wiring grooves
US6812127B2 · kind B2 · utility
21Cited by
13References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2001 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Nov 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interlayer dielectric film that surrounds via holes for connecting wirings of a second wiring layer and the wirings of third wiring layer is constituted of a dielectric material having a relatively smaller Young's modulus compared with the Young's modulus of a dielectric material constituting a dielectric film that surrounds wiring grooves in dual damascene wirings, which can improve the heat resistance and electromigration resistance of the dual damascene wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.