Patent · US Expired

Recessed metal lines for protective enclosure in integrated circuits

US6812141B1 · kind B1 · utility

16Cited by
2References
32Claims
0Family size

Assignees

Inventors

Key dates

Filing dateJul 1, 2003
Grant dateNov 2, 2004
Priority date
Expiry dateJul 1, 2023

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B61/00
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.