High density floating gate flash memory and fabrication processes therefor
US6812514B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode, at least one of sidewall/spacers, second sidewalls or a barrier layer, in which the floating gate is positioned above the channel region. The floating gate may be separated from the channel region by one or more of a reverse tunnel dielectric layer, the barrier layer and a pad dielectric layer. The floating gate may be a metal floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.