Massively parallel interface for electronic circuits

US6812718B1 · kind B1 · utility

Assignee

• Nanonexus, Inc. · US

Inventors

• Fu Chiung Chong · Saratoga, US
• Sammy Mok · Cupertino, US

Key dates

• Filing date: Nov 21, 2001
• Grant date: Nov 2, 2004
• Expiry date: Nov 21, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2874
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel intergrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connection between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabrication spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector component…