Entering test mode and accessing of a packaged semiconductor device
US6812726B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48139
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system is provided for testing a first integrated circuit chip to be packaged along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of test buffer multiplexer circuits. Each test buffer multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each test buffer multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.