Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators
US6812758B2 · kind B2 · utility
26Cited by
9References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 12, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Feb 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.