Bias distribution network for digital multilevel nonvolatile flash memory
US6813194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells arranged in rows and columns with a portion of the rows of the memory cells being divided into segments. A global bias circuit generates a plurality of first bias currents. Each of a plurality of local bias networks includes a local bias circuit that generates a plurality of second bias currents in response to a corresponding one of the plurality of first bias currents, and includes a plurality of segment bias circuits that each generates a third bias current. Each segment bias circuit is adjacent to a corresponding segment of the memory cells. Each segment bias circuit provides a ground feedback signal to the local bias circuit, which adjusts the second bias current in response to the ground feedback signal. The segment bias circuits are disposed in geometric positions in the segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.