Method of simultaneous display of die and wafer characterization in integrated circuit technology development
US6815233B1 · kind B1 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.