Reducing stress in integrated circuits
US6815234B2 · kind B2 · utility
4Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.