Ultra-thin fully depleted SOI device and method of fabrication
US6815297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jan 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A fully depleted SOI FET and methods of formation are disclosed. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source, a drain and a body disposed between the source and the drain are formed from the layer of semiconductor material. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess. The gate defines a channel in the body and includes a gate electrode spaced apart from the body by a high-K gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.