Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing
US6815345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/24
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.