Circuit configuration for the bit-parallel outputting of a data word
US6816094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the bits of the data word to driver stages and to a reference circuit. Further driver stages are connected in parallel with the driver stages and have inputs connected to the control device. The control device establishes the signal states of the data signals to be transferred on each signal line and generates a control signal depending on the type and number of the signal state changes of bit sequences to be transferred. It is possible to drive the driver stages that assigned to the signal line for which a signal state change is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.